Principles of Decoupling Networks Part 3

In this post I will discuss some guidelines for location and number of decoupling caps for a generic PDN.

How close should the capacitors in a decoupling network be to the power pins they serve? One way to answer that is to think about it in terms of how quickly a decoupling capacitor can respond to a change in voltage on the power plane. When an IC switches internally it demands current from the power plane. The power plane can’t provide the current instantaneously so the voltage starts to drop at the power pin. This drop needs to propagate to the nearest decoupling cap before the cap can start to respond and bring the voltage back up. That response then must travel back to the power pin of the IC. There are two round trip delays before the power pin gets relief. A cap placed too far away from the power pin can’t respond in time to the transient event. As the cap is placed closer to the power pin the energy transmitted to the power pin increases until it hits 100% at 0 distance. If the cap is more than a quarter wavelength away from the power pin it essentially provides no relief. We can achieve efficient energy transfer at some fraction of 1/4 λ from the power pin. For example, one tenth of quarter λ is a good target ( placement radius = λ /40).

We know that a capacitor’s resonant frequency is given by the following.

Fres = 1/2 π√LC  

The period of that resonant frequency is:

Tres = 1/Fres  

Physics tells us that a wave’s speed is the wavelength divided by the wave’s frequency.  Or alternatively:

λ = Tres/Vprop

Where Vprop is the propagation delay (sec/inch) of a board with a given dielectric.  For microstrip FR-4 connections this is about 140 ps/inch.

If we use a .001 uF MLCC cap in an 0402 package with a mounted inductance of 2.0 nH as our high frequency decoupling we can calculate λ = 63.5 inches.  Using our desired placement radius from above of  λ/40 tells us that we need to place this cap within 1.59 inches of the power pin.   That’s not so bad! We don’t need to stuff them all on the back of the board under the IC’s footprint unless we want to.  It is desirable to keep them close to the power/gnd plane sandwich to minimize inductance.  This could be on either side of the board. 

Larger value capacitors have correspondingly lower resonant frequencies and a higher placement radius.  A 1 uF capacitor, for example, can go just about anywhere on the board and still be effective. The following table shows capacitance versus placement radius. 

CapacitanceResonant FrequencyPlacement Radius
1 nF112.5 Mhz1.59 inches
10 nF35.6 Mhz5.02 inches
100 nF11.3 Mhz15.8 inches
1 uF3.6 Mhz50.1 inches
10 uF1.1 Mhz158.67 inches
100 uF356 Khz501.77 inches
1000uF112.5 Khz1586.74 inches

So how many decoupling capacitors do we really need? As noted earlier we want to use a broad mixture of capacitor values to approximate our desired flat PDN impedance. I have successfully used a formula that roughly doubles the quantity of capacitors for every decade decrease in value. The following table illustrates the scheme.

CapacitanceQuantity PercentageExample Capacitor Type
470 to 1000 uF 4%Tantalum
1.0 to 4.7 uF 14%X7R 0805
0.1 to 0.47 uF 27%X7R 0603
0.01 to 0.047 uF 55%X7R 0402

So, for example, if I have an IC with 10 active power pins I would use six 0.01 uF caps placed within an inch of the pins close to the power plane, three 0.1 uF caps and one 1.0 uF cap nearby. In a corner of the board I would place a 470uF Tantalum cap. If I added another of the same type of IC to the design I would add five more .01 uF caps, two 0.1 uF caps, and one 1.0 uF cap. I would share the 470uF Tantalum cap between multiple ICs.