Decoupling is the technique used to reduce switching noise in the Power Distribution Network. CMOS transistors draw current when they are switching. This sudden current draw leads to a voltage drop or ripple on the power plane of the circuit board. The ideal PDN provides a low impedance path to minimize the voltage ripple on the power plane.
The diagram below shows an ideal low impedance PDN along with the frequency bands where various parts of the PDN respond. At low frequencies the power supply is the dominant current supplier. Between the KHz and MHz ranges low frequency or bulk decoupling caps provide the energy needed. Between the MHz and Ghz bands high frequency decoupling takes over and finally the capacitance of the board’s power planes is most effective at very high frequencies.
A real capacitor is usually modeled as a series R-L-C circuit. When you plot its impedance versus log frequency you get a picture similar to that shown below.
The left side of the V is due to the capacitive reactance and the right side of the V is due to parasitic inductance. The notch of the V is the resonance point where the impedance is given by the capacitor’s equivalent series resistance. Since we know that
V = I / 2πFC
and capacitors in parallel add we can decrease ripple voltage by adding capacitors in parallel to the PDN. A different value of capacitance will have the V centered at a different frequency. If you compare the above V shaped response to the ideal PDN impedance we are trying to achieve you can see a problem though. How do we turn the V shaped response into the flat response we want? If we put capacitors of various values in parallel we can take a step in the right direction. The idea is to use a bunch of V’s at different frequencies to approximate a U-shaped frequency response. This works well as long as you watch out for a phenomenon called anti-resonance. Anti-resonance arises from the right side of the V shape for one capacitor over-lapping the left side of the V shape for another capacitor. Where they sum you get a lump of increased impedance. Anti-resonance can be managed by using low inductance capacitors and many different values of capacitors.
Our first rule is then: put numbers of different value capacitors in parallel and minimize the inductance. We need to minimize inductance because we know that
V = 2πFL x I
Which tells us that to minimize ripple voltage at high frequencies reducing the inductance is more effective than increasing the capacitance.
The inductance of a capacitor mounted on a circuit board includes the capacitor’s parasitic inductance and additional inductance from the loop the current traverses from the power plane to the cap and back to the ground plane as shown below. So how you mount your decoupling capacitors matters as well.
What are some low inductance ways to mount a capacitor?
The above diagram shows various combinations of pads, trace, and vias. The ones towards the right side of the diagram minimize inductance. Short fat trace minimizes inductance. For example, I prefer 10 mil trace for power in many cases. Larger diameter vias have less inductance. The shorter the via the less inductance also. In some designs putting the vias inside the component’s pads is an option. This can lead to problems assembling a circuit board though– in-pad vias can act like little straws and suck up the solder paste– so I didn’t include it here.
So far we know that we need a variety of capacitors with different capacitance values. We need capacitors with low parasitic inductance and they must have low inductance connections to the power plane. There is one other element to consider– the placement of the capacitors. I’ll talk about that in my next post.