I was sitting in my office with a fresh cup of coffee and a bag of donuts contemplating which donut to eat first. As I pondered the merits of a jelly filled beauty covered in sprinkles I noticed the sprinkles looked like tiny surface mount decoupling capacitors on a circuit board. I have seen high speed digital designs with no decoupling capacitors. The designer swore it would work because he had sandwiched the respective power and ground planes in such a clever fashion. It didn’t. And I have seen people put so many caps on a board they looked like a Bedazzler project. That one worked but the layout person threatened homicide.
As I ate my donut I thought about all the myths and superstitions surrounding power decoupling I have heard over the years. It seems to me that a designer’s approach to power decoupling can tell you a lot about their personality. I participate in a lot of design reviews. The people in the reviews are usually much more interesting than the designs. Whether they are bent on proving to the world how clever they are or just obsessive about rules they may not understand fully often shows up in how they approach keeping the power rails clean.
A Power Distribution Network (PDN) consists of the power supply, power/ground planes, power traces, and decoupling capacitors. The purpose of a decoupling capacitor is to provide clean power to the devices on a circuit board. Power consumed by digital devices varies over time. Most chip manufacturers specify the cleanliness of that power. For example, +/-5% is a common specification for a power pin. This fixes the maximum amount of noise or “ripple voltage” that can ride on power supply traces. The ripple voltage comes from current switching within the devices on the board. Low frequency ripple usually comes from chips being enabled or disabled. This type of ripple can happen on a time scale from milliseconds to days. I once found one that happened every 3 hours or so and resulted in a bus protocol violation that powered down the board. High frequency ripple comes from current switching within a device and the time scale is related either to the clock period or a higher harmonic.
A full-blown detailed PDN design encompasses SPICE modelling and analysis followed by prototype measurements using a scope or network analyzer. Verifying the accuracy of the models used is essential. This work can take quite a bit of time and money and is really only needed in extreme cases. Most of the time a less time consuming approach is acceptable. This approach uses a good decoupling strategy guided by experience that allows you to quickly produce a working prototype you can then experiment with to reduce cost and make the boss smile.
Engineering always involves trade-offs between time, risk, and money. Engineers who last in the business always leave some wiggle room for unexpected error. As I said to the engineer mentioned above who designed a board with no decoupling: “What happens if you don’t have a decoupling network and you are wrong?” It doesn’t take much time or effort to put in a basic decoupling network if you understand the principles. And you can easily experiment with removing capacitors or changing values once you have the prototype. He proceeded to cost his employer a lot of money by producing an unreliable prototype with no capacitors and hard to debug noise problems, and then had to re-layout the board. A good strategy for PDN design in most cases does not have to be overly time consuming to implement. A few guidelines based on experience can speed things up.
So what are some guidelines that lead to happy results? That’s where we are going. To set the stage for that though I need to delve a little deeper into what the decoupling network is really doing. Next Post.