In previous posts we’ve talked about how an FPGA based SOC in your system allows hardware changes to be made late in the design cycle or even in the field thus helping reduce time-to-market and increase time-in-market. In today’s post we talk about some of the advantages an FPGA based SOC provides the system designer.
Most embedded electronic systems are composed of processors, peripherals, memory, and lot’s of software. Today’s system-on-chip (SOC) FPGA based systems provide significant advantages in processing and in how peripherals are used.
Today’s SOC FPGAs offer many options to customize processing so you can optimize performance, power dissipation, and cost in your system. The first decision usually confronted is the choice between a hard-core versus soft-core processor. Performance is often the key issue but cost is always a consideration of course. Most hard-core processors are targeted at higher-end, pricier, FPGAs. Soft-core processors can be used in less expensive FPGAs as well as the higher performance/higher priced silicon. Hard-cores provide higher performance but are tied to a particular chip or chip family that may be discontinued by its manufacturer some day. For long-lived systems this can be a huge problem. For some applications the lower performance of a soft-core processor is preferable because it can be placed in a new chip when an old one goes end-of-life.
Selecting an SOC FPGA based processor is not as simple as just comparing MIPS between two processors though. SOC FPGAs are capable of implementing a variety of distributed processing architectures. Processors embedded in FPGAs today can communicate via high performance parallel or serial busses. Soft-core processor performance can often be enhanced with the use of co-processors to perform critical tasks. Most packet processing today is done with multiple specialized processors running in parallel for example. At Black Brook Design, we’ve implemented different types of co-processors from simple state machines to complex micro-programmed sequencers. The options available to system designers today were only dreamed of ten years ago.
For many signal and image processing applications the ability to perform complex algorithms in high speed hardware is essential. Such applications can often use a lower performance “control plane processor” to manage the system while running the critical algorithms in FPGA gates at high speed.
Optimizing and customizing the processor’s peripherals is another important area of concern. System designers can save cost by integrating as many peripherals as possible in the SOC FPGA. In most cases it’s relatively easy to change the numbers and types of peripherals as well as modify peripherals to allow things like custom test functions, loopback logic, packet snooping, etc. And perhaps most important, is the ability to add custom peripherals.
All this capability comes at the cost of increased complexity and risk though. It’s our old friend the customization/complexity coin from an earlier post. With so many options in hardware and software it’s easy for development schedules to go “off the rails”. A soft appliance based solution solves this problem by providing an off-the-shelf FPGA bitstream with the processor(s), many common peripherals, and the software pieces needed to boot and run Linux– all integrated together. Whether it’s based on a hard or soft core, getting a control plane processor to boot up and communicate is a great way to jump start development. Your development resources can be focused on the real value add in your system– application development– instead of working to solve low level hardware and software issues.