# Principles of Decoupling Networks Part 3

In this post I will discuss some guidelines for location and number of decoupling caps for a generic PDN.

How close should the capacitors in a decoupling network be to the power pins they serve? One way to answer that is to think about it in terms of how quickly a decoupling capacitor can respond to a change in voltage on the power plane. When an IC switches internally it demands current from the power plane. The power plane can’t provide the current instantaneously so the voltage starts to drop at the power pin. This drop needs to propagate to the nearest decoupling cap before the cap can start to respond and bring the voltage back up. That response then must travel back to the power pin of the IC. There are two round trip delays before the power pin gets relief. A cap placed too far away from the power pin can’t respond in time to the transient event. As the cap is placed closer to the power pin the energy transmitted to the power pin increases until it hits 100% at 0 distance. If the cap is more than a quarter wavelength away from the power pin it essentially provides no relief. We can achieve efficient energy transfer at some fraction of 1/4 λ from the power pin. For example, one tenth of quarter λ is a good target ( placement radius = λ /40).

We know that a capacitor’s resonant frequency is given by the following.

Fres = 1/2 π√LC

The period of that resonant frequency is:

Tres = 1/Fres

Physics tells us that a wave’s speed is the wavelength divided by the wave’s frequency.  Or alternatively:

λ = Tres/Vprop

Where Vprop is the propagation delay (sec/inch) of a board with a given dielectric.  For microstrip FR-4 connections this is about 140 ps/inch.

If we use a .001 uF MLCC cap in an 0402 package with a mounted inductance of 2.0 nH as our high frequency decoupling we can calculate λ = 63.5 inches.  Using our desired placement radius from above of  λ/40 tells us that we need to place this cap within 1.59 inches of the power pin.   That’s not so bad! We don’t need to stuff them all on the back of the board under the IC’s footprint unless we want to.  It is desirable to keep them close to the power/gnd plane sandwich to minimize inductance.  This could be on either side of the board.

Larger value capacitors have correspondingly lower resonant frequencies and a higher placement radius.  A 1 uF capacitor, for example, can go just about anywhere on the board and still be effective. The following table shows capacitance versus placement radius.

 Capacitance Resonant Frequency Placement Radius 1 nF 112.5 Mhz 1.59 inches 10 nF 35.6 Mhz 5.02 inches 100 nF 11.3 Mhz 15.8 inches 1 uF 3.6 Mhz 50.1 inches 10 uF 1.1 Mhz 158.67 inches 100 uF 356 Khz 501.77 inches 1000uF 112.5 Khz 1586.74 inches

So how many decoupling capacitors do we really need? As noted earlier we want to use a broad mixture of capacitor values to approximate our desired flat PDN impedance. I have successfully used a formula that roughly doubles the quantity of capacitors for every decade decrease in value. The following table illustrates the scheme.

 Capacitance Quantity Percentage Example Capacitor Type 470 to 1000 uF 4% Tantalum 1.0 to 4.7 uF 14% X7R 0805 0.1 to 0.47 uF 27% X7R 0603 0.01 to 0.047 uF 55% X7R 0402

So, for example, if I have an IC with 10 active power pins I would use six 0.01 uF caps placed within an inch of the pins close to the power plane, three 0.1 uF caps and one 1.0 uF cap nearby. In a corner of the board I would place a 470uF Tantalum cap. If I added another of the same type of IC to the design I would add five more .01 uF caps, two 0.1 uF caps, and one 1.0 uF cap. I would share the 470uF Tantalum cap between multiple ICs.

# Basic Principles of Power Decoupling Networks Part 2

Decoupling is the technique used to reduce switching noise in the Power Distribution Network.  CMOS transistors draw current when they are switching.  This sudden current draw leads to a voltage drop or ripple on the power plane of the circuit board.  The ideal PDN provides a low impedance path to minimize the voltage ripple on the power plane.

The diagram below shows an ideal low impedance PDN along with the frequency bands where various parts of the PDN respond.  At low frequencies the power supply is the dominant current supplier.  Between the KHz and MHz ranges low frequency or bulk decoupling caps provide the energy needed.  Between the MHz and Ghz bands high frequency decoupling takes over and finally the capacitance of the board’s power planes is most effective at very high frequencies.

Ideal PDN Impedance

A real capacitor is usually modeled as a series R-L-C circuit. When you plot its impedance versus log frequency you get a picture similar to that shown below.

The left side of the V is due to the capacitive reactance and the right side of the V is due to parasitic inductance.  The notch of the V is the  resonance point where the impedance is given by the capacitor’s equivalent series resistance.  Since we know that

V = I / 2πFC

and capacitors in parallel add we can decrease ripple voltage by adding capacitors in parallel to the PDN. A different value of capacitance will have the V centered at a different frequency.  If you compare the above V shaped response to the ideal PDN impedance we are trying to achieve you can see a problem though.  How do we turn the V shaped response into the flat response we want? If we put capacitors of various values in parallel we can take a step in the right direction.  The idea is to use a bunch of V’s at different frequencies to approximate a U-shaped frequency response.  This works well as long as you watch out for a phenomenon called anti-resonance.  Anti-resonance arises from the right side of the V shape  for one capacitor over-lapping the left side of the V shape for another capacitor.  Where they sum you get a lump of increased impedance.  Anti-resonance can be managed by using low inductance capacitors and many different values of capacitors.

Our first rule is then:  put numbers of different value capacitors in parallel and minimize the inductance.  We need to minimize inductance because we know that

V = 2πFL x I

Which tells us that to minimize ripple voltage at high frequencies reducing the inductance is more effective than increasing the capacitance.

The inductance of a capacitor mounted on a circuit board includes the capacitor’s parasitic inductance and additional inductance from the loop the current traverses from the power plane to the cap and back to the ground plane as shown below.    So how you mount your decoupling capacitors matters as well.

Capacitor Loop Current

What are some low inductance ways to mount a capacitor?

The above diagram shows various combinations of pads, trace, and vias.  The ones towards the right side of the diagram minimize inductance.  Short fat trace minimizes inductance.  For example, I prefer 10 mil trace for power in many cases.  Larger diameter vias have less inductance.  The shorter the via the less inductance also.  In some designs putting the vias inside the component’s pads is an option.  This can lead to problems assembling a circuit board though– in-pad vias can act like little straws and suck up the solder paste–  so I didn’t include it here.

So far we know that we need a variety of  capacitors with different capacitance values.  We need capacitors with low parasitic inductance and they must have low inductance connections to the power plane.  There is one other element to consider– the placement of the capacitors.  I’ll talk about that in my next post.

# Basic Principles of Power Decoupling Networks Part 1

I was sitting in my office with a fresh cup of coffee and a bag of donuts contemplating which donut to eat first.  As I pondered the merits of a jelly filled beauty covered in sprinkles I noticed the sprinkles looked like tiny surface mount decoupling capacitors on a circuit board.   I have seen high speed digital designs with no decoupling capacitors.  The designer swore it would work because he had sandwiched the respective power and ground planes in such a clever fashion.  It didn’t.   And I have seen people put so many caps on a board they looked like a Bedazzler project.  That one worked but the layout person threatened homicide.

As I ate my donut I thought about all the myths and superstitions surrounding power decoupling I have heard over the years.  It seems to me that a designer’s approach to power decoupling can tell you a lot about their personality.  I participate in a lot of design reviews.  The people in the reviews are usually much more interesting than the designs. Whether they are bent on proving to the world how clever they are or just obsessive about rules they may not understand fully often shows up in how they approach keeping the power rails clean.

A Power Distribution Network (PDN) consists of the power supply, power/ground planes, power traces, and decoupling capacitors.  The purpose of a decoupling capacitor is to provide clean power to the devices on a circuit board.  Power consumed by digital devices varies over time.  Most chip manufacturers specify the cleanliness of that power. For example, +/-5% is a common specification for a power pin. This fixes the maximum amount of noise or “ripple voltage” that can ride on power supply traces.  The ripple voltage comes from current switching within the devices on the board.  Low frequency ripple usually comes from chips being enabled or disabled.  This type of ripple can happen on a time scale from milliseconds to days.  I once found one that happened every 3 hours or so and resulted in a bus protocol violation that powered down the board.  High frequency ripple comes from current switching within a device and the time scale is related either to the clock period or a higher harmonic.

A full-blown detailed PDN design encompasses SPICE modelling and analysis followed by prototype measurements using a scope or network analyzer.  Verifying the accuracy of the models used is essential.  This work can take quite a bit of time and money and is really only needed in extreme cases.  Most of the time a less time consuming approach is acceptable.   This approach uses a good decoupling strategy guided by experience that allows you to quickly produce a working prototype you can then experiment with to reduce cost and make the boss smile.

Engineering always involves trade-offs between time, risk, and money.  Engineers who last in the business always leave some wiggle room for unexpected error.  As I said to the engineer mentioned above who designed a board with no decoupling: “What happens if you don’t have a decoupling network and you are wrong?”  It doesn’t take much time or effort to put in a basic decoupling network if you understand the principles.  And you can easily experiment with removing capacitors or changing values once you have the prototype.  He proceeded to cost his employer a lot of money by producing an unreliable prototype with no capacitors and hard to debug noise problems, and then had to re-layout the board.  A good strategy for PDN design in most cases does not have to be overly time consuming to implement.  A few guidelines based on experience can speed things up.

So what are some guidelines that lead to happy results?  That’s where we are going.  To set the stage for that though I need to delve a little deeper into what the decoupling network is really doing.   Next Post.

# Tradecraft: Source Synchronous Bus Timing Problem

Interfacing to a source synchronous bus with an FPGA can be a bit tricky.  Today’s FPGA tools provide lots of resources to help achieve timing closure inside the chip.  Sometimes though, the FPGA needs a little help external to the chip to meet timing.

I recently ran into a case where an FPGA connected to an Ethernet PHY over a GMII bus.  The GMII bus uses simplex point to point connections for transmit and receive.  The source end of the connection drives the clock.  Both the clock and data for the GMII “Transmit” connection were sourced from the FPGA.  Close inspection of the FPGA timing report revealed that the data could come out 118 picoseconds before the clock came out. It is important that both the setup and hold time requirements of the PHY be met.

It was necessary to ensure the clock arrived at the PHY before the data lines changed (zero hold time) and that the PHY’s setup time requirements were met.   The easiest way to do this was to delay the data lines a small fixed amount by running them as longer nets than the clock line.   This ensures most of the clock period for setup time at the PHY and still maintains a 0 ns hold time.    The exact board propagation delay number is based on the dielectric constant of the circuit board and can be calculated by a circuit board vendor given the details of a board.   My general rule of thumb for delay in a stripline trace is about 165 ps/inch.  Sometimes a little propagation delay is a good thing!